In the production of monolithic integrated circuit chips, many elements are typically produced in the surface layer of the chip. These elements may comprise resistors, diodes, NPN or PNP bipolar transistors or insulated-gate field effect transistors of the N or P channel type, as examples. The several elements, when completed, are connected together to provide such circuit components as flip-flop circuits, digital logic circuit elements, or memory circuits, to name but a few. Then the circuit building blocks are connected together to provide a functional circuit, and the circuit input and output terminals are connected to external terminals through the pads on the chip.
All the connections between the elements that do not cross are typically made in a single level. That is, a layer of insulation, typically oxide, is provided either during construction of the elements of the chip, or in a later step over the exposed surface of the chip that contains the many circuit elements. Holes are provided in this layer to permit making connections to the elements. Patterned conductors are then applied to the surface of the insulating layer as necessary to provide the connections that can be most efficiently made without crossing any of the lines.
Then a second layer of insulation is put over the first layer of conductors. Holes are made in the second layer of insulation to permit connections to points on the first layer of connections or to the underlying substrate where the circuit elements are located. Then a second layer of conductors is applied over the second layer of insulator. This second layer crosses the first layer as is necessary but is insulated therefrom by the second layer of insulation. This process is repeated as often as the circuit design complexity and performance requires.
As the elements in the underlying substrate become smaller and smaller, and the circuits become denser and more complicated, these wiring connections have effectively come into play as imposing limits on the packing density of elements which can be achieved. In fact, in some complex chips the metal lines occupy a larger fraction of the total chip surface area than the active elements in the substrate because of the complexity of the interconnections and the need to separate the lines sufficiently to avoid capacitance, cross talk and related fabrication problems.
The typical approach to forming the connecting lines in today's technology is to sputter aluminum or an alloy of aluminum over the dielectric surface and then pattern and etch the aluminum. After one layer of metal is in place, the dielectric is put down over it. This results in problems with achieving planarization of the surface of the dielectric layer. Such planarization is necessary to be able to get accurate lithography in defining the placement of the upper layers of connections over the surface of the dielectric because with a lack of planarization, the depth of fecus to the surface of the integrated circuit will change for spatially distributed points on the chip. Moreover, achieving a planarized surface layer helps to improve the circuit yield and scalability.
Past efforts to overcome this problem have focused on putting a layer of oxide over each layer of metal lines and then spinning on glass or photo resist. This layer, since it is fluid, can be processed to harden into a relatively smooth surface. However, this requires additional baking, and etching and deposition steps to achieve the proper thickness of the planarized oxide dielectric between metal layers, and can be an expensive, time consuming and difficult process to reliably reproduce.
Further, as the width of the aluminum wires used to define the circuit patterns is scaled down to the submicron regime, problems are created in handling the required current densities through these extremely fine metal line widths. That is, at high current densities, metal lines can be cut open or adjacent metal lines can short together because of movement of the atoms of aluminum caused by the momentum of the electrons established by the high current densities (electromigration failures).
It has been found that metals such as tungsten are much more resistant to problems such as electromigration failures described above. However, tungsten offers a resistance level that is about two times higher than that of aluminum. Therefore, the problem becomes to incorporate a sufficient thickness of tungsten to define a metal interconnect line having relatively low resistance without creating even greater planarization problems than those posed by the use of aluminum lines.
A further problem is to avoid the need for dry etching or plasma etching of the metal lines which is used to transfer the desired pattern of the lines to the surface of the integrated circuit.